Implementing cable failover in multiple cable PCI Express IO interconnections

ABSTRACT

A method, system and computer program product are provided for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections to an external IO enclosure. System firmware is provided for implementing health check functions for the PCIE IO interconnections to identify a faulted low byte cable. A cable failover mechanism recovers a PCI link to the external IO enclosure. A multiplexer logic is provided between the PCIE host bridge (PHB) and the cable connected to the IO enclosure to perform a full lane reversal of the PCIE lanes.

This application is a continuation application of Ser. No. 14/924,617 filed Oct. 27, 2015.

FIELD OF THE INVENTION

The present invention relates generally to the data processing field, and more particularly, relates to a method, system and computer program product for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections.

DESCRIPTION OF THE RELATED ART

Peripheral Component Interconnect Express (PCIE) has become the industry standard IO bus for server computer systems, as well as personal computers (PCs). Traditionally, servers install PCIE IO adapters (IOAs) in slots within a system unit that connect through a PCI host bridge to the system memory and processor buses. IBM POWER and Z series systems have offered external IO enclosures to provide additional PCIE slots beyond those that are available within the system unit. These have in the past been connected to the system unit through IBM proprietary interconnect architectures such as HSL and Infiniband 12× IO loops on IBM POWER systems.

A typical PCIE bus is a simple board path from the PCIE host bridge (PHB) and the IO adapter (IOA). When using optical cables for attaching an external IO drawer the complexity of the path is greatly increased with the various components in the path which include PCIE retimers, optical transceivers (CXPs) that convey PCIE signals over optical channels and cables. The components in this optical path do not always have clear failure mechanisms that can be used to help determine where the fault in the PCIE path is to indicate to firmware what optical channels are at fault.

A need exists for an effective and efficient mechanism for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections in a computer system.

SUMMARY OF THE INVENTION

Principal aspects of the present invention are to provide a method, system and computer program product implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections in a computer system. Other important aspects of the present invention are to provide such method, system and computer program product substantially without negative effects and that overcome many of the disadvantages of prior art arrangements.

In brief, a method, system and computer program product are provided for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections to an external IO enclosure. System firmware is provided for implementing health check functions for the PCIE IO interconnections to identify a faulted low byte cable. A cable failover mechanism recovers a PCI link to the external IO enclosure. A multiplexer logic is provided between the PCIE primary host bridge (PHB) and the cable connected to the IO enclosure to perform a full lane reversal of the PCIE lanes.

In accordance with features of the invention, when the entire low byte cable (PCIE lanes 0-7) has failed or is unplugged, the full lane reversal of the PCIE lanes of the high byte and the low byte cable enable recovery. PCI express requires the lanes to be functional in sequential order, so if PCI lane 0 is not functional then a functioning PCI connection to the downstream device is not enabled.

In accordance with features of the invention, the lanes are changed from a 0-15 configuration to 15-0. The result of this configuration change is that PCIE lanes 0-7 are now carried in the functional high cable and can form a functional PCIE link.

In accordance with features of the invention, the PCIE link runs with half the normal configuration in a degraded state, but allows the connection to function until the customer is able to service the faulty cable and restore full width.

In accordance with features of the invention, firmware detects through health check failures in the low cable to determine when lane reversal should be provided.

In accordance with features of the invention, the PCIE lane multiplexers are configured to reversed mode and the PCIE links are retrained to the downstream device.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:

FIG. 1 illustrates an example computer system for detecting status and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channel attached to an IO drawer and implementing a sideband control structure for Peripheral PCIE input/output (IO) expansion enclosures or IO drawers in accordance with a preferred embodiment;

FIGS. 2A, and 2B illustrates cable card and sideband controls of the example system of FIG. 1 in accordance with a preferred embodiment;

FIGS. 3A, and 3B illustrates further details of Local and Remote FPGA Controllers of the example system of FIG. 1 in accordance with a preferred embodiment;

FIG. 4 illustrates example operational features of a physical layer view of I2C multiplexer (MUX) and data engine at host side and IO drawer end of the example system of FIG. 1 in accordance with a preferred embodiment;

FIG. 5 is a flow chart illustrating example firmware operational features using sideband status information of the example system of FIG. 1 in accordance with a preferred embodiment;

FIGS. 6A and 6B together illustrate example PCI bus topology of the example system of FIG. 1 in accordance with a preferred embodiment;

FIG. 7 illustrate example lane sparing hardware of the example system of FIG. 1 in accordance with a preferred embodiment;

FIG. 8 is a flow chart illustrating example operations for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections to an external IO enclosure in accordance with a preferred embodiment; and

FIG. 9 is a block diagram illustrating a computer program product in accordance with the preferred embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which illustrate example embodiments by which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

In accordance with features of the invention, a method, system and computer program product are provided for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections to an external IO enclosure in accordance with a preferred embodiment. System firmware is provided for implementing health check functions for the PCIE IO interconnections to identify a faulted low byte cable. A cable failover mechanism recovers a PCI link to the external IO enclosure. A multiplexer logic is provided between the PCIE primary host bridge (PHB) and the cable connected to the IO enclosure to perform a full lane reversal of the PCIE lanes.

In accordance with features of the invention, when the entire low byte cable (PCIE lanes 0-7) has failed or is unplugged, the full lane reversal of the PCIE lanes of the high byte and the low byte cable enable recovery. PCI express requires the lanes to be functional in sequential order, so if PCI lane 0 is not functional then a functioning PCI connection to the downstream device is not enabled. In accordance with features of the invention, the lanes are changed from a 0-15 configuration to 15-0. The result of this configuration change is that PCIE lanes 0-7 are now carried in the functional high cable and can form a functional PCIE link.

Having reference now to the drawings, in FIG. 1, there is shown an example computer system generally designated by the reference character 100 for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections to an external IO enclosure in accordance with a preferred embodiment. Computer system 100 includes a computer Central Electronics Complex (CEC) 102 that includes a system motherboard 104 common in the art that provides for the physical packaging interconnection of the various components illustrated within the CEC 102. Computer system 100 includes an input/output (IO) expansion enclosure or IO drawer generally designated by the reference character 106 in accordance with a preferred embodiment.

In accordance with features of the invention, the IO drawer 106 is an electrical enclosure that provides PCIE add-in card slots (PCIE slots) or integrated devices utilized by firmware and software operating within the CEC 102 to extend the number of PCIE devices physically configurable within the scope of the CEC.

CEC system motherboard 104 includes one or more processors or central processor units (CPUs), such as processor 110. Processor 110 is suitably arranged for executing firmware and software, such as operating system and applications hosted by respective operating systems in control of the overall computer system 100 in accordance with a preferred embodiment.

CEC system motherboard 104 includes one or a plurality of PCIE root complexes 120. Each PCIE root complex 120 includes one or a plurality of PCIE host bridges (PHBs) 130, each PHB 130 providing a respective PCIE link 132 to a respective PCIE slot 134 mounted commonly on the system motherboard 104. For example, the PCIE link 132 is comprised of a plurality of 16 lanes of PCIE signaling wires and auxiliary signals, such as specified in the PCIE standard. The auxiliary signals include PCIE PERST, also called Fundamental Reset, and PCIE clocks from the PHB 130 to a PCIE device, PCIE card present from a device to a PHB 130, and other such discrete signals that operate independently of the PCIE signaling lanes.

One or more of the PCIE slots 134 includes a respective PCIE cable card 140 including a PCIE lane multiplexer (mux) logic 141 connected with a respective PCIE cable connector 142 connected by a pair of PCIE cables 144 to a corresponding respective PCIE cable connector 142 provided with the IO drawer 106, as shown. While the PCIE lane multiplexer (mux) logic 141 is shown with the cable card 140, it should be understood the present invention is not limited to this arrangement. For example, the PCIE lane multiplexer (mux) logic 141 advantageously could be provided inside the PHB 130. Also the PCIE lane multiplexer (mux) logic 141 advantageously could be provided outside the PCIE switch 156 of a fan-out module or fan-out bay 154.

In accordance with features of the invention, the PCIE lane mux logic 141 contains PCIE lane muxes to reverse the PCIE lane assignments from the PHB 130 to the external PCIE cables 144 and logic to control the muxes through system firmware.

IO drawer 106 includes one or a plurality of module bays, such as a direct slot bay 150 including a plurality of PCIE slots 152, and a fan-out bay 154, including a PCIE switch 156 connected to another plurality of PCIE slots 152, as shown. Each of the direct slot bay 150, PCIE slots 152, and the fan-out bay 154 is connected to the CEC 102 by the individual and independent cables 144 via PCIE cable connectors 142, as shown. The PCIE switch 156 includes an upstream port 158 connected upstream to the PCIE Cable Connector 142 and downstream to a plurality of downstream ports 160, each connected to a respective PCIE slot 152, as shown.

In accordance with features of the invention, the downstream PCIE devices, such as the PCIE switch or adapters 156 support the same maximum lane width, such as 16 lanes, as the PHB 130. The downstream PCIE devices or PCIE switch or adapters 156 support running in normal (0-15) and lane reversed (15-0) modes. downstream PCIE devices or PCIE switch or adapters 156 support the PCIE lane reversal mode. Also the PCIE lane multiplexer (mux) logic 141 could be added to the direct slot bay 150.

In accordance with features of the invention, firmware detects, for example, through health check failures in the low cable to determine when lane reversal should be provided. Firmware can configure the PCIE lane mux logic 141 to a reversed mode and retrain the PCIE links to the downstream device, such as PCIE switch 156.

Computer system 100 is shown in simplified form sufficient for understanding the present invention. The illustrated computer system 100 is not intended to imply architectural or functional limitations. The present invention can be used with various hardware implementations and systems and various other internal hardware devices.

In accordance with features of the invention, one or a plurality of cables 144 is provided with each cable card 140 and respective PCIE slot 152 or PCIE switch 156. As shown, a pair of PCIE cables 144 convey PCIE signal lanes and auxiliary signals forming a single PCIE link, and the PCIE cables 144 also convey sideband control and status signals between the CEC 102 and the IO drawer 106. The use of two cables 144 for each single PCIE link between the CEC 102 and IO drawer 106 advantageously enables redundancy in the event of a cable failure. Only a single cable 144 is utilized in communicating sideband controls and status between the CEC and IO drawer, and each of the two cables 144 provides an alternative signaling path to communicate such sideband controls. In accordance with a preferred embodiment, the invention utilizes a pair of cables to carry PCIE signals and redundant status and control signals. Other embodiments may utilize more than two cables to carry either or both PCIE signal lanes and redundant sideband status and controls between a cable card 140 in a CEC 102 and a slot 152 or switch 156 in an IO drawer 106. A plurality of cables forming a single link is advantageous to provide sideband signal redundancy; however, other embodiments may utilize a single cable, having spare optical channels within that single cable, to obtain the optical channel failure, sideband signal redundancy, and sparing objectives of the invention.

In accordance with features of the invention, the cables 144 may be conventional copper cables or fiber optic cables employing opto-electronic transceivers at each cable end. For example, with relatively short distances, such as inches to a few feet, copper cables 144 are generally suitable for conveying PCIE lanes operating at required PCIE signaling rates between the CEC 102 and IO drawer 106. Optical cables 144 advantageously provide electrical isolation to enable high signaling rates over longer distances, such as one to many meters.

In accordance with features of the invention, use of optical PCIE cables 144 includes serializing required DC signals over the optical cables 144 and then converting the serialized signals back to DC signals at the other end of the optical PCIE cables 144 at CEC 102 or the IO drawer 106.

In accordance with features of the invention, firmware operating in the CEC 102 is enabled to determine a type of cable card 140 plugged into a PCIE slot 134, with a plurality of different such cable card types having differing properties, such as whether the cables 144 are copper or optical, how many cables 144 emanate from the cable card 140, and the like. It is similarly advantageous for firmware operating in the CEC 102 to be able to determine whether the cables 144 are actually connected to an IO drawer 106, and what type of IO drawer 106, and the IO module bay 150, or module bay 156, is connected to cables 144.

In accordance with features of the invention, in a logically partitioned computer system 100 firmware operating in the CEC 102 is enabled to assign respective CEC PCIE slots 134 to a particular logical partition when that slot 134 contains a PCIE IO adapter. Computer system 100 firmware operating in the CEC 102 is further enabled to detect a cable card 140 in a PCIE slot 134 and to assign respective CEC PCIE slots 152 of an IO drawer 106 to different logical partitions with the cable card 140 connected to an IO drawer 106.

Referring also to FIGS. 2A, and 2B, additional example details of novel cable card 140 and sideband controls generally designated by the reference character 201 are shown of computer system 100 of FIG. 1 in accordance with a preferred embodiment. As shown in FIG. 2A, included within or accessible to the processor 110 is an Inter-Integrated Circuit (I2C) master device 202, which is the master of an I2C bus 204 utilized as an IO bus of the sideband signaling apparatus of a preferred embodiment. It should be understood that other such IO buses or sideband control structures known in the art may be suitable to substitute for the I2C bus 204 utilized by the invention. Within CEC 102, the I2C bus 204 is connected between the I2C master device 202 and a card present port expander 206, PCIE slots 134, a vital product data (VPD) chip 208, and a local control field programmable gate array (FPGA) 210 provided within the cable card 140.

The PCIE cable card 140 utilizes pins within the PCIE connector 142 of the PCIE slot 134 defined in PCIE as reserved pins to generate a signal identifying the PCIE cable card 140 as a cable card. The card present port expander 206 connected on the I2C bus 204 receives a card present signal from the cable card 140 uniquely indicating the presence of a cable card, as opposed to a PCIE IO adapter. Firmware operating in the CEC 102 utilizes the I2C master 202 to read registers within the card present port expander 206 in order to determine that the cable card 140 is plugged in the respective PCIE card slot 134. It should be understood that devices other than the card present port expander 206 could be used to receive cable card present information in a manner accessible to firmware operating within the CEC 102.

The local control FPGA 210 includes registers that receive status from and optionally signal controls to other hardware components located on the cable card 140. The registers within the local control FPGA 210 are connected to the I2C bus 204 proceeding from the PCIE slot 140 onto the cable card 140.

Referring also to FIG. 2B, the IO drawer 106 similarly includes a remote control FPGA 250. The remote control FPGA 250 includes registers that receive signals from other hardware components internal to the IO drawer 106. The IO drawer 106 includes a drawer controller 252 coupled to the remote control FPGA 250 via an I2C bus 254.

In accordance with features of the invention, as shown in FIGS. 2A, and 2B, sideband controls 201 are coupled between the local control FPGA 210 in the CEC 102 and the remote control FPGA 250 in IO drawer 106 by a low byte cable 260 and a high byte cable 262. For example, the low byte cable 260 conveys PCIE lanes 0 through 7 of the PCIE link from the PCIE slot 134, shown as Low Byte PCIE 264, and conveys sideband signals between the cable card 140 and the IO drawer 106, shown as Low Byte Control 266. For example, the high byte cable 262 conveys PCIE lanes 8 through 15 of the PCIE link from the PCIE slot 134, shown as High Byte PCIE 268, and conveys sideband signals between the cable card 140 and the IO drawer 106, shown as High Byte Control 270. For example, the high byte cable 262 serves as an alternate or redundant connection to the low byte cable 260 for the purpose of conveying sideband signals.

Using either the low byte control 266 or high byte control 270, the remote control FPGA 250 signals changes in the states of various hardware components or DC voltage signals within the IO drawer 106 to the local control FPGA 210, which receives these changes in registers accessible to firmware operating in the CEC 102. Similarly, firmware operating in the CEC 102 may set register values in the local control FPGA 210 directed at the remote control FPGA 250 to change the state of hardware components or DC voltage signals within the IO drawer 106.

Using the either the low byte control 266 or high byte control 270, the local FPGA 210 communicates local FPGA 210 register changes to the remote control FPGA 250. The registers within the remote control FPGA 250 connect to the I2C bus 254 within the IO drawer 106. The remote FPGA registers are also accessible as I2C devices from the local control FPGA 210. Firmware operating in the CEC 102 utilizes registers in the local control FPGA 210 to create I2C bus operations transmitted between the local control FPGA 210 and remote control FPGA 250 utilizing the low byte control 266 or high byte control 270. The local control FPGA 210 enables firmware operating within the CEC 102 to determine various configuration and operational states of hardware components or DC voltage signals located on the cable card 210 as well as hardware components or DC voltage signals within the IO drawer 106.

The drawer controller 252 connected to the remote control FPGA 250 within the IO drawer 106 monitors or manages states of the hardware internal to the IO drawer, such as turning on or off power supplies within the drawer, monitoring thermal or electrical states of components within the drawer, taking actions in response to particular thermal or electrical states or thresholds, and the like. The drawer controller 252 connects to the remote control FPGA 250 utilizing the I2C bus 370, enabling the drawer controller 252 to read or write registers within the remote control FPGA 250 and to communicate status to or receive control information communicated from the local control FPGA 210 using the low byte control 266 or high byte control 270.

Referring also to FIGS. 3A, and 3B, additional example details of local control and remote control FPGAs 210, 250 are shown of the example system 100 of FIG. 1 in accordance with a preferred embodiment.

The cable card 140 is shown connected to the IOA drawer 106 utilizing a low byte cable 302 and a high byte cable 304. The low byte cable 302 conveys the low byte PCIE signals 306 representing PCIE lanes 0 to 7 and control signals between the local FPGA 210 and remote FPGA 250 indicated as low byte control 308. The high byte cable 304 conveys the high byte PCIE signals 310 representing PCIE lanes 8 to 15 and control signals between the local FPGA 210 and remote FPGA 310 indicated as high byte control 312. The signals conveyed by means of the low byte control 308 and high byte control 312 signals may be communicated over either or both of the low byte cable 302 and the high byte cable 304 at any one time, such that each cable can convey the control signals as a backup for the other in the event of failure or disconnection of one cable 302 or 304, and such that signals may be communicated simultaneously over both cables in order to detect the location to which each cable is connected at the IO drawer 106.

The low byte control 308 and low byte PCIE 306 signals in the low byte cable 302, and the high byte control 312 and high byte PCIE 310 signals in the high byte cable 304 are conveyed optically utilizing a respective optical transceiver (XCVR) 318 on the cable card 140 and optical transceiver (XCVR) 358 in the IO drawer 106. The PCIE lanes 0 to 7 conveyed on the low byte PCIE 306 and lanes 8 to 15 conveyed on the high byte PCIE 310 commonly pass through a PCIE re-timer 320 in FIG. 3A, a PCIE re-timer 360 in FIG. 3A in order to synchronize them with the respective optical transceivers 318, 358 shown in FIGS. 3A and 3B.

The local control FPGA 210 on the cable card 140 includes a local FPGA data engine 322, registers 324, a link engine 326, and a wire engine 328. The remote control FPGA 250 similarly includes a remote FPGA data engine 362, registers 364, a link engine 366, and a wire engine 368, and optionally a flash memory 370 coupled to the data engine 362. The local control FPGA data engine 322 and remote control FPGA data engine 362 are capable of exchanging control signals utilizing either the low byte control 308 or high byte control 312 conveyed over the low byte cable 302 or high byte cable 304, respectively. The local control FPGA 210 link engine 326 utilizes the data engine 322 to establish reliable optical signaling and bit transfer protocols between the optical XCVRs 318 on the cable card 140 and the optical XCVRs 358 and data engine 362 in the IO drawer 106 over both of the low byte cable 302 and high byte cable 304.

The wire engine 328 of local control FPGA 210 receives the state of certain bits of the registers 324 or DC voltage signals and utilizes the data engine 322 to transmit these states to the registers 364 of the remote control FPGA 250. The registers 324 include a predefined bit to assert the state of the PCIE auxiliary PERST DC voltage signal output from a PHB 130 to a device attached to the respective PCIE link, and a bit to receive the state of PCIE auxiliary device present DC voltage signal from a PCIE slot 152 or PCIE switch 156 in the IO drawer 106 connected to the PCIE link over the low byte cable 302 and high byte cable 304. When the state of certain bits of registers 324 changes, the wire engine 328 of the local control FPGA 210 automatically communicates these to registers 364 of the remote FPGA 250. The wire engine 368 of remote control FPGA 250 receives the state of certain bits of the registers 364 or DC voltage signals and utilizes the data engine 362 to transmit these states to the registers 324 of the local control FPGA 210. Whenever the state of these certain bits of registers 364 changes, the wire engine 368 automatically communicates these to registers 324 of the local control FPGA 210.

The respective wire engine 328, 368 on each end of the optical cables 302, 304 provide an alternative signaling mechanism for PCIE auxiliary signals or other DC voltage signals within the fiber optic cables to establish or receive the active or inactive state of the auxiliary signals at the respective other end of the cable.

The registers 324 of local control FPGA 210 include bits representing various properties of the cable card 140, such as the type of the cable card itself, the type and connection states of the low byte cable 302 and high byte cable 304. The registers 324 of the local control FPGA 210 include bits to detect the states of certain hardware inputs from or control the states of certain hardware outputs to the components of the cable card 140. The registers 324 of local control FPGA 210 include bits representing various properties of the cable connections to that TO drawer, such as representing which location on the TO drawer 106 of the low byte cable 302 and high byte cable 304 are connected, to enable firmware to determine that cables are properly connected.

The cable card 140 and the TO drawer 106 optionally includes Link Active LEDs 380 in association with each of the low byte cable 302 and high byte cable 304. Firmware operating in the CEC 102 utilizes bits within the registers 324 of the local control FPGA 210 to active or deactivate the link active LEDs 380 to indicate that the cable is or is not actively transmitting signals between the cable card 140 and IO drawer 106. It should be understood that hardware mechanisms may alternatively be utilized to detect link transmission activity and to accordingly activate or deactivate link active LEDs 380. Firmware operating in the CEC 102 performs other control and communications operations, such as activating or deactivating power to the IO drawer 106, a bay 150, or a bay 154, PCIE slots 152, or other components within the IO drawer 106.

Referring to FIG. 4, there are shown example operational features generally designated by the reference character 400 of a physical layer view of the example system 100 of FIG. 1 in accordance with a preferred embodiment. An I2C multiplexer (MUX) 402 connects to an I2C bus 406 and a respective data engine 404, 414 and an I2C SPI flash logic 410, 420 at host side FPGA 210 and IO drawer side FPGA 250 are shown connected by CXP lanes. A respective SPI flash 412, 422 is coupled to the I2C SPI flash 410, 420 at host side FPGA 210 and IO drawer side FPGA 250. The I2C multiplexer (MUX) 402 and the respective data engine 404, 414 enable system firmware to access secondary I2C buses in either the host FPGA 210 or IO drawer FGPA 240 in a consistent manner. The secondary I2C bus could be one of the I2C buses 254 of FIG. 3B communicating to I2C devices within the IO drawer 106 or it could be one of the I2C buses 204 of FIG. 3A communicating to the I2C devices of the cable card 140.

Referring to FIG. 5, there is shown a flow chart illustrating example firmware operational features using sideband status information of the example system 100 in accordance with a preferred embodiment.

As indicated in a decision block 500, checking for a PCIE card present in CEC PCIE slot is performed. When a PCIE card is not present in CEC PCIE slot, then operations return as indicated in a block 501. When a PCIE card is present in CEC PCIE slot, the cable card present port expander is read as indicated in a block 502. As indicated in a decision block 504, again checking for the PCIE cable card present in CEC PCIE slot is performed. When a PCIE cable card is not present in CEC PCIE slot, then operations return at block 501.

When a PCIE cable card is present in CEC PCIE slot, the local FPGA registers are read to get cable status and connection locations as indicated in a block 506. Checking if the cable card includes a pair of cables or dual cables is performed as indicated in a decision block 508. When the cable card includes dual cables, checking is performed to determine if the high byte control is working as indicated in a decision block 510. If the high byte control is not working, a cable error is logged for service as indicated in a block 512. If the high byte control is working and when the cable card does not include dual cables, checking is performed to determine if the low byte control is working as indicated in a decision block 514. If the low byte control is not working, a cable error is logged for service as indicated in a block 516.

As indicated in a block 518, local FPGA registers are read to verify cables are correctly connected low to low, high to high, and same PCIE link connection at the IO drawer. Checking if cabled correctly is performed as indicated in a decision block 520. If not cabled correctly, a cable error is logged for service as indicated in a block 522. If cabled correctly, PERST to the IO drawer PCIE link connection is de-asserted as indicated in a block 524. Checking is performed to determine if connected to PCIE switch in IO drawer as indicated in a decision block 526. When connected to PCIE switch in IO drawer, the PCIE switch and downstream PCIE links to PCIE slots in the IO drawer are configured as indicated in a block 528. The PCIE slot or PCIE slots in the IO drawer under the PHB connected to this cable are configured as indicated in a block 530 following block 528 and following decision block 526 if not connected to PCIE switch in IO drawer. The PCIE link connection configuration is complete as indicated in a block 532.

Referring to FIGS. 6A and 6B, there is shown example PCI bus generally designated by the reference character 600 of the example system 100 in accordance with a preferred embodiment. The illustrated PCI bus 600 provides a path from a PCIE host bridge (PHB) 602 to an optical cable attached IO drawer 106. For example, two industry standard 12 lane optical cables are used to carry PCIE and sideband traffic between the system PHB 602 and the IO drawer 106. Each cable contains 8 lanes of PCIE traffic, 1 channel of sideband communication and 1 spare optical channel with two channels unused. With one cable carrying PCIE lanes 0-7 (low byte) and the other carrying PCI lanes 8-15 (high byte) together they make an x16 PCIE bus connection to the IO drawer 106. The one spare optical channel per cable in each direction allows firmware to route a single PCIE lane away from a faulted channel to the spare channel when firmware determines a channel that is faulted. Other implementations could use, for example two unused channels as spares for the PCIE links as well. Other embodiments could also use, for example, more than 2 cables each cable carrying fewer than 8 of the 16 PCIE bus signal lanes, and spare optical channels for those lanes, and two or more of those cables also carrying redundant sideband communication signals.

As shown in FIG. 6A, PCI bus 600 includes a PCIE retimer 604, field programmable gate array (FPGA) communication devices 606, lane sparing multiplexers (muxes) 608 including lane sparing transmit (TX) muxes 610, and lane sparing receive (RX) muxes 612, and High and Low optical module transceivers (CXPs) 614, 616 with respective optical connections X9+DN, SB, X9+UP, SB. With respect to the cable card end of the cable X9+DN represents nine PCIE optical transmit channels, eight active plus one spare, and X9+UP represents nine PCIE optical receive channels, eight active plus one spare, and wherein each transmit channel is paired with a receive channel to form a single bi-directional PCIE lane. For example, with each industry standard optical cable containing 12 channels of bidirectional traffic, eight of those channels optionally are used for PCIE, one used for sideband communication SB and one of the three unused channels wired to be used as a spare PCIE lane. As shown, the FPGA communication devices 606 are connected to the PCIE retimer 604, High and Low optical module transceivers (CXPs) 614, 616, and the lane sparing multiplexers (muxes) 608.

As shown in FIG. 6B, PCI bus 600 includes High and Low optical module transceivers (CXPs) 620, 620 that are connected to the High and Low optical module transceivers (CXPs) 614, 616 of FIG. 6A with the respective optical connections X9+DN, SB, X9+UP, SB. With respect to the IO drawer end of the cable, X9+DN represents nine PCIE optical transmit channels, eight active plus one spare, and X9+UP represents nine PCIE optical receive channels, eight active plus one spare, and wherein each transmit channel is paired with a receive channel to form a single bi-directional PCIE lane. PCI bus 600 includes lane sparing multiplexers (muxes) 624 including lane sparing transmit (TX) muxes 626, and lane sparing receive (RX) muxes 628; a PCIE retimer 630, field programmable gate array (FPGA) communication devices 632, and a PCIE switch 634 of the IO drawer 106. As shown, the PCIE switch 634 is connected to a plurality of PCI slots 636 #1-N, for example, 6 PCI slots 636 of the IO drawer 106. As shown, the FPGA communication devices 632 are connected to the PCIE retimer 630, High and Low optical module transceivers (CXPs) 620, 620, lane sparing multiplexers (muxes) 624, and connected to the PCIE switch 634, a drawer controller (CMC) 638 and the PCI slots 636 of the IO drawer 106.

Referring to FIG. 7 there is shown example lane sparing hardware generally designated by the reference character 700 of the example system 100 in accordance with a preferred embodiment. Lane sparing hardware 700 is used to reroute PCIE lanes to a spare optical channel on both ends of the optical path in accordance with a preferred embodiment. As shown, lane sparing hardware 700 includes an I2C port expander device 702 coupled to an optical transceiver (CXP) connector 704 by a CXP interface block 706.

The I2C port expander device 702 is used to control a set of PCIE lane multiplexers (muxes) 708, 710. As shown, lane sparing hardware 700 includes a retimer 714 coupled to the PCIE lane muxes 708, 710, a field programmable gate array (FPGA) 716 coupled by sideband and SM bus to the CXP interface block 706 and CXP connector 704 and coupled to the I2C port expander device 702. Lane sparing hardware 700 includes control and status registers 718 included with the CXP connector 704.

Interrogating PCIE retimers in either the cable card 140 or IO drawer 206 ends of a cable, such as retimer 714 can be used to determine a faulted optical channel. For example, by reading retimer registers it is possible to determine for each PCI lane what stage of the PCIE link training sequence has been initiated. System firmware can use this information to determine if one lane has not progressed at all which then indicates a bad optical channel. By reading transmit status registers in the optical transceivers of either the cable card 140 or IO drawer 106 it is possible to determine for each optical channel if a fault has occurred. This information can be used to determine a bad optical channel. By reading receiver status registers 718 in the optical transceivers 704 of the IO drawer 106 it is possible to detect a loss of signal from the respective cable card 140 transceiver and this information can be used to determine a bad optical channel.

By programming muxes in the PCIE path firmware can reroute PCIE away from the faulted channel. The I2C port expander device 702 is controlled through the FPGA 716, for example using I2C communication through the sideband signals. When the I2C port expander device 702 is programmed by firmware it changes the input to output mapping of the PCIE lane muxes 708, 710 which causes the PCIe bus to be rerouted down a different optical channel. When the operation is complete a reset sequence can be initiated on the PCIE bus incorporate the spare channel into the link to recover to its optimal width.

Referring to FIG. 8, there are shown example operations for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections in accordance with a preferred embodiment starting the PCIE link health check as indicated in a block 800. Checking is performed, for example, periodically or as a result of a hardware interrupt to determine if the PCIE link is degraded, as indicated in a decision block 802. When the PCIE link is not degraded, then the operations are completed as indicated in a block 804. When the PCIE link is degraded components are interrogated to determine if a faulted low byte cable exists as indicated in a block 806.

Checking is performed to determine if a faulted low byte cable is detected as indicated in a decision block 808. When a functional high byte cable is not detected, then the operations are completed as indicated in a block 810.

When a faulted low byte cable is detected, components are interrogated to determine if a functional high byte cable exists as indicated in a block 812. Checking is performed to determine if a functional high byte cable is detected as indicated in a decision block 814. When a functional high byte cable is not detected, then the operations are completed as indicated in a block 816.

When a functional high byte cable is detected, then a PERST is asserted to the PCIE link as indicated in a block 818. The low byte cable is disabled as indicated in a block 820. The PCI host bridge (PHB) is reconfigured to reverse the PCIE lane order as indicated in a block 822. The PERST is deasserted and the PCIE links are retrained as indicated in a block 824. The operations are completed as indicated in a block 826.

It would be obvious to extend the sequences of FIG. 5, and FIG. 8 and the structures of FIGS. 6A, 6B, and 7 to an embodiment utilizing more than 2 cables between a cable card 140 in a CEC 102 and a slot 152 or switch 156 in an IO drawer 106. It would be obvious to extend the present invention to signaling or IO interconnections other than PCIE where optical cabling is utilized to convey such signals.

Referring now to FIG. 9, an article of manufacture or a computer program product 900 of the invention is illustrated. The computer program product 900 is tangibly embodied on a non-transitory computer readable storage medium that includes a recording medium 902, such as, a floppy disk, a high capacity read only memory in the form of an optically read compact disk or CD-ROM, a tape, or another similar computer program product. Recording medium 902 stores program means 904, 906, 908, and 910 on the medium 902 for carrying out the methods for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCI-Express or PCIE) IO interconnections attached to an IO drawer 106 of preferred embodiments in the system 100 of FIG. 1.

A sequence of program instructions or a logical assembly of one or more interrelated modules defined by the recorded program means 904, 906, 908, and 910, direct the computer system 100 for implementing cable failover in multiple PCIE IO interconnections attached to an IO drawer 106 of a preferred embodiment.

While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims. 

What is claimed is:
 1. A computer system for implementing cable failover in a PCIE link including multiple cable Peripheral Component Interconnect Express (PCI-Express or PCIE) IO interconnections attached to an IO drawer, comprising: a processor; system firmware provided with said processor; a PCIE host bridge (PHB); said PHB connected to said processor; the PCIE link including multiple cable PCIE IO interconnections coupled between said PCIE host bridge (PHB) and an PCIE enclosure with a respective Inter-Integrated Circuit (I2C) bus conveying IO control signaling; PCIE multiplexer logic coupled between said PHB and the multiple cable PCIE IO interconnections coupled to the PCIE enclosure; said processor using said system firmware for periodically implementing health check functions and responsive to a hardware interrupt to determine if the PCIE link is degraded; said processor using said system firmware responsive to detecting a degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying a functional high byte cable, and identifying a faulted low byte cable, performing a full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure; and said processor using said system firmware, running the PCIE link in a degraded state with half a normal configuration until the PCIE cable is serviced to restore full width.
 2. The system as recited in claim 1, wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware implementing health check functions for the PCIE IO interconnections to identify the degraded link.
 3. The system as recited in claim 1, wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware for implementing health check functions for the PCIE IO interconnections to identify a functional high byte cable.
 4. The system as recited in claim 1, wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware for interrogating components to determine if a functional high byte cable exists.
 5. The system as recited in claim 1, wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware implementing health check functions for the PCIE IO interconnections to identify the faulted low byte cable.
 6. The system as recited in claim 1, wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware for interrogating components to determine if a faulted low byte cable exists.
 7. The system as recited in claim 1, wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware, disabling the low byte cable.
 8. The system as recited in claim 1, wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware, reconfiguring the PHB to reverse the PCIE lane order.
 9. The system as recited in claim 1, wherein said processor using said system firmware responsive to detecting the degraded PCIE link using the PCIE multiplexer logic and said respective I2C bus conveying IO control signaling, identifying the functional high byte cable, and identifying the faulted low byte cable, performing the full lane reversal of the PCIE lanes for recovering the PCIE link to the PCIE enclosure includes said processor using said system firmware, detecting link transmission activity. 